Method of manufacturing semiconductor device

ABSTRACT

To enhance and/or improve reliability in a method of forming a semiconductor device. An exemplary method of forming a semiconductor device forms a conductive part within a concave portion which is formed in a first surface of a semiconductor substrate. The semiconductor substrate includes an integrated circuit. The method also thins the substrate by removing a part of a second surface of the semiconductor substrate so as to make the conductive part penetrate from the first surface to the second surface, and cuts the semiconductor substrate into pieces. An electric property of the semiconductor substrate is inspected through the conductive part after the conductive part is formed.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method of manufacturing asemiconductor device.

2. Description of Related Art

The related are includes a semiconductor device with three-dimensionalmounting. Also, in accordance with the related art, a penetratingelectrode is formed on a semiconductor substrate, and more than onesemiconductor substrate is stacked-up, and then the penetratingelectrode formed on a upper substrate and the penetrating electrodeformed on a lower substrate are coupled. In a related art method, aninspection process checking an electric property of the semiconductorsubstrate is conducted before the penetrating electrode is formed. Inthe inspection process, since an end terminal of an inspection toolcontacts with the electrode (an aluminum pad), a trace sometimes remainson the surface of the electrode. This decreases reliability in formingthe penetrating electrode, and it can lead to a lower yield of thesemiconductor device.

The related art also includes a device disclosed in Japanese UnexaminedPatent Publication No. 2002-359347.

SUMMARY OF THE INVENTION

An exemplary embodiment of the invention addresses the above-mentionedand/or other problems, and enhances and/or improves reliability in amethod of forming a semiconductor device.

An exemplary method of manufacturing a semiconductor device of thepresent invention includes (a) forming a conductive part within aconcave portion that is formed in a first surface of a semiconductorsubstrate having an integrated circuit, (b) thinning the semiconductorsubstrate by removing a part of a second surface of the semiconductorsubstrate so as to make the conductive part penetrate from the firstsurface to the second surface, (c) cutting the semiconductor substrateinto pieces. The method may also include inspecting an electric propertyof the semiconductor substrate through the conductive part followingstep (a). In accordance with the above-described exemplary method ofmanufacturing a semiconductor device, since an electric property of thesemiconductor substrate is checked after the formation process of theconductive part, the inspection process does not adversely affectreliability in the formation process of the conductive part.Consequently, reliability of the method of manufacturing a semiconductordevice will be enhanced and/or improved.

In the exemplary method of manufacturing a semiconductor device, theconductive part may be formed to have a brazing layer on its top surfacein step (a). For example, the brazing layer is soft so that an endterminal of an inspection tool can securely contact with the conductivepart without slipping. Even if a trace is marked on the top surface partof the conductive part when the end terminal contacted, the mark can bereduced or eliminated by melting at least a part of the brazing layer ina later process.

In the exemplary method of manufacturing a semiconductor device, theconductive part may be formed to have a gold layer on its top surface instep (a). For example, the gold layer is soft so that an end terminal ofan inspection tool can securely contact with the conductive part withoutslipping. Even if a trace is marked on the top surface part of theconductive part when the end terminal contacted, the mark can be reduceor eliminated by melting at least a part of the gold layer in a laterprocess.

In the exemplary method of manufacturing a semiconductor device, theinspecting process may be conducted before step (b). This will make ahandling of the semiconductor substrate easier compared to a case whichthe inspection process is carried out after the thinning process. Inparticular, it can prevent the semiconductor substrate from beingimpaired.

In the exemplary method of manufacturing a semiconductor device, step(c) may further include (c1) providing a reinforcing member on thesemiconductor substrate, (c2) conducting the inspecting process and (c3)cutting the semiconductor substrate. As such, a handling of thesemiconductor substrate may be easier since the semiconductor substrateis reinforced with the reinforcing member. In particular, it may preventthe semiconductor substrate from being impaired.

In the exemplary method of manufacturing a semiconductor device, thereinforcing member has a tape applied to one of the first surface or thesecond surface and a supporting member which supports the tape. Theexemplary method of manufacturing a semiconductor device may includestacking a plurality of semiconductor devices which are manufacturedusing the above-mentioned exemplary method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through D are schematics that show a method for manufacturing asemiconductor device according to an exemplary embodiment of the presentinvention;

FIGS. 2A through D are schematics that show the method for manufacturinga semiconductor device according to the exemplary embodiment of thepresent invention;

FIGS. 3A through D are schematics that show the method for manufacturinga semiconductor device according to the exemplary embodiment of thepresent invention;

FIG. 4 is a schematic that shows the method for manufacturing asemiconductor device according to the exemplary embodiment of thepresent invention;

FIG. 5 is a schematic that shows an electric apparatus according to anexemplary embodiment of the present invention; and

FIG. 6 is a schematic that shows an electric apparatus according to anexemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary of the present invention are described below with reference tothe accompanying figures. FIG. 1A through FIG. 4 show a method ofmanufacturing a semiconductor device according to an exemplaryembodiment of the present invention.

A semiconductor substrate 10 (for example, a silicon substrate) isprovided. The semiconductor substrate 10 may be a semiconductor wafer ora semiconductor chip. On the semiconductor substrate 10, an integratedcircuit 12 is formed. In a case of the semiconductor wafer, theintegrated circuit 12 is provided in the plural number (see FIG. 3A). Ina case of the semiconductor wafer, a single of the integrated circuit 12is formed. An electrode 14 (for example, a pad) electrically coupledwith the integrated circuit 12 is formed on the semiconductor substrate10. The electrode 14 is provided in the plural number to each integratedcircuit 12. The electrode 14 of provided in the plural number may bearranged along edges of the integrated circuit 12 (for example, at twofacing sides or four sides of its rectangular area). The electrode 14 ismade of a metal, such as aluminum or copper, and formed to be thin andflat. According to this exemplary embodiment of the present invention,the electrode 14 is not used for checking an electric property in aninspection process, so that the electrode 14 is hardly damaged.Therefore, reliability in forming a penetrating electrode (a conductivepart 30) will be enhanced and/or improved, and thereby the yield ratioof the semiconductor device will also be enhanced and/or improved. Thepenetrating electrode will be described in detail later.

A passivation film 16 and another passivation film 18, each film made upof one layer or more, are formed on the semiconductor substrate 10. Thepassivation films 16 and 18 may be formed of SiO2, SiN, polyimide resinand the like. In the example shown in FIG. 1A, the electrode 14 and awiring (not shown in the figures) which connects the integrated circuit12 and the electrode 14 are formed on the passivation film 16. Thepassivation film 18 is formed at least avoiding a part of the surface ofthe electrode 14. The passivation film 18 may be formed to cover thewhole surface of the electrode 14 as long as a part of the passivationfilm 18 is removed later by etching, for example, so as to expose partof the surface of the electrode 14. Either dry etching or wet etchingmay be applied to the etching. The surface of the electrode 14 may beetched when the passivation film 18 is etched.

In this exemplary embodiment, a concave portion 22 (see FIG. 1C) whichstarts from a first surface 20 of the semiconductor substrate 10 isformed in the semiconductor substrate 10. The first surface 20 is asurface on which the electrode 14 (or the integrated circuit 12) isformed. The concave portion 22 is formed avoiding elements and wiringsof the integrated circuit 12. As shown in FIG. 1B, a through-hole 24 maybe formed in the electrode 14. Etching (dry etching or wet etching) maybe applied to form the through-hole 24. The etching may be performedafter a resist (not shown in the figures) patterned by photolithographyis formed. If the passivation film 16 is formed under the electrode 14,a through-hole 26 (see FIG. IC) is also formed in the passivation film16. If the etching of the electrode 14 stops at where the passivationfilm 16 is, another etchant, which is different from one used foretching the electrode 14, can be used to form the through-hole 26. Inthat case, another resist (not shown in the figures) patterned byphotolithography may be formed.

As shown in FIG. 1C, the concave portion 22 is formed in thesemiconductor substrate 10 to communicate with the through-hole 24 (andthe through-hole 26). The through-hole 24 (and the through-hole 26) aswell as the concave portion 22 can be called as a concave portion.Etching (dry etching or wet etching) may be also applied to form theconcave portion 22. The etching may be performed after a resist (notshown in the figures) patterned by photolithography is formed.Alternatively, a laser (for example, a CO2 laser, an Yttrium AluminumGarnet laser (YAG) and the like) may be applied to form the concaveportion 22. The laser may also be applied to form the through-holes 24and 26. The concave portion 22, the through-holes 24 and 26 may beformed consecutively with a single type of etchant or laser. A sandblastprocessing may be applied to form the concave portion 22.

As shown in FIG. 1D, an insulating layer 28 may be formed inside theconcave portion 22. The insulating layer 28 may be an oxide film or anitride film. For example, if the semiconductor substrate 10 is made ofSi, the insulating layer 28 may be made of SiO2 or SiN. The insulatinglayer 28 is formed on the bottom surface and inner wall of the concaveportion 22. However, the insulating layer 28 is formed not to fill upthe concave portion 22, in other words, the insulating layer 28 forms aconcave portion. The insulating layer 28 may be formed on the inner wallof the through-hole 26 that is formed in the passivation film 16. Theinsulating layer 28 may also be formed on the passivation film 18.

Further, the insulating layer 28 may be formed on the inner wall of thethrough-hole 24 that is formed in the electrode 14. The insulating layer28 is formed avoiding a part of the surface of the electrode 14 (forexample, its upper surface). The insulating layer 28 may be formed tocover the whole surface of the electrode 14 as long as a part of theinsulating layer 28 is removed later by etching (dry etching or wetetching) so as to expose part of the electrode 14. The etching may beperformed after a resist (not shown in the figures) patterned byphotolithography is formed.

Next, the conductive part 30 (see FIG. 2D) is formed in the concaveportion 22 (for example, inside the insulating layer 28). The conductivepart 30 may consist of a single layer or multiple layers. In theexemplary embodiment, the conductive part 30 includes a foundation part32, a central part 34 and a top surface part 36. As shown FIG. 2A, thecentral part 34 is formed after forming the foundation part 32 in theconductive part 30. The upper surface of the central part 34 (on whichthe top surface part 36 is formed) is formed to be flat. The centralpart 34 may be formed of Cu, W or doped polysilicon (for example,low-temperature polysilicon). The foundation part 32 may include atleast a barrier layer. The barrier layer reduces and/or prevents amaterial of the central part 34 or a seed layer that will be describedbelow from diffusing into the semiconductor substrate 10 (made of Si,for example). The barrier layer may be formed of a different kind ofmaterial (for example, TiW, TiN) from that of the central part 34. Whenthe central part 34 is formed by electroplating, the foundation part 32may include a seed layer. The seed layer is formed after forming thebarrier layer. The seed layer can be formed of the same material as thatof the central part 34 (for example, Cu). The conductive part 30 (or atleast its central part 34) can be formed by electroless planting or inkjetting.

As shown in FIG. 2B, if the foundation part 32 is formed on thepassivation film 18, a part of the foundation part 32 which is placed onthe passivation film 18 (and the insulating film 28) is etched as shownin FIG. 2C.

As shown in FIG. 2D, the top surface part 36 is formed on the outside(for example, the upper surface) of the central part 34. The top surfacepart 36 may be a brazing layer formed of a brazing material. In otherwords, the conductive part 30 may be formed to have the brazing layer inits top surface 36. The brazing layer may be formed of solder, forexample, either a soft solder or a hard solder can be used. The brazinglayer may be formed while covering the area other than the upper surfaceof the central part 34 with a resist. As a modification, the top surfacepart 36 may be a gold layer including at least gold (Au).

As described above, the conductive part 30 is formed. A part of theconductive part 30 is placed within the concave portion 22 of thesemiconductor substrate 10. Since the insulating layer 28 is interposedbetween the inner wall of the concave portion 22 and the conductive part30, an electrical connection between the two is not available. Theconductive part 30 is electrically coupled with the electrode 14 (theintegrated circuit 12). For example, the conductive part 30 may contactwith an exposed part of the electrode 14 from the insulating layer 28.Also, the conductive part 30 may be formed only in the area of theelectrode 14. Further, the conductive part 30 may project at least abovethe concave portion 22. For example, the conductive part 30 may projectfarther than the passivation film 18 (and the insulating layer 28). Asan exemplary modification, the central part 34 may be formed as thefoundation part 32 remains on the passivation film 18. In that case, alayer communicating with the central part 34 is formed over thepassivation film 18 and should be etched.

According this exemplary embodiment, the inspection process of checkingan electric property of the semiconductor substrate 10 is conductedafter forming the conductive part 30. This makes it possible to detectdefects in the integrated circuit 12, the electrode 14, the conductivepart 30 and the like. When a defect is found, it is preferable that itis marked. As shown in FIG. 3A, in the inspection process checking anelectric property, an end terminal 42 (for example, a needle) of aninspection tool 40 (for example, a probe) is brought into contact withan electric contact area of the semiconductor substrate 10 while theinspection is conducted. The end terminal 42 may be brought into contactwith the conductive part 30 (the top surface part 36 in FIG. 3A). Atrace of the end terminal 42 may remain on the surface of the conductivepart 30. When the top surface part 36 is made of a brazing layer (or agold layer), the end terminal 42 can securely contact with theconductive part 30 and be retained at the position without slippingsince the brazing layer (or the gold layer) is soft. Consequently, theinspection process becomes more reliable. If at least a part of the topsurface part 36 is melted in a later process (for example, a mountingprocess of the semiconductor device), the trace on the top surface part36 which is marked when the end terminal 42 contacted can be reducedand/or eliminated, so that reliability of the semiconductor device willnot be decreased.

As shown in FIG. 3A, the inspection process checking the electricproperty may be carried out before a thinning process of thesemiconductor substrate 10 (see FIG. 3B) in which the thickness of thesemiconductor substrate 10 is reduced. It will make it easier to handlethe semiconductor substrate 10 (for example, transport to an inspectionstage) than a case in which the inspection process follows the thinningprocess of the semiconductor substrate 10. More specifically, it mayprevent the semiconductor substrate 10 from being impaired (cracking andthe like).

It is preferable that in the inspection process, checking the electricproperty of the semiconductor substrate 10 is not conducted before theformation process of the conductive part 30 (for example, at a pointwhen the integrated circuit 12 and the electrode 14 are formed). In thisway, the contact trace of the end terminal 42 will not be left on thesurface of the electrode 14 and it improves and/or enhances reliabilityin the formation process of the conductive part 30 (for example, alithography process).

As shown in FIG. 3B, a part of the semiconductor substrate 10 is removedfrom its second surface 21 and the semiconductor substrate 10 is made tobe thinner. For example, this can be performed by at least one chemicalor mechanical grinding process. The surface of the semiconductorsubstrate 10 may be ground and polished with a grind stone, or may beetched. The thinning process of the semiconductor substrate 10 can bebroken into several steps. For example, at a first step of the thinningprocess, the semiconductor substrate 10 may be ground and polished rightbefore the insulating layer 28, in the concave portion 22, is going tobe exposed. Then at the following steps of the thinning process, theinsulating layer 28 may be exposed. The second surface 21 of thesemiconductor substrate 10 may be etched in such a way that theconductive part 30 (more specifically, a part of the conductive part 30which is within the concave portion 22) protrudes as it is covered withthe insulating layer 28. The etching may be conducted with an etchantworks more on the semiconductor substrate 10 (of Si, for example) thanon the insulating layer 28 (of SiO2, for example). The etchant may beSF6, CF4, or C12 gas. The etching may be carried out with a dry-etchingapparatus. Also, the etchant may be a compound liquid of hydrofluoricacid and nitric acid or of hydrofluoric acid, nitric acid and aceticacid.

As described above, the conductive part 30 penetrates from the firstsurface 20 to the second surface 21. The conductive part 30 is called asa penetrating electrode. The conductive part 30 protrudes from at leastone of the first surface 20 and the second surface 21 (in FIG. 3B, fromthe both surfaces). A protruding part of the conductive part 30 from thesecond surface 21 may be covered with the insulating layer 28. In thiscase, the conductive part 30 is exposed from the insulating layer 28 ina later process. Or the conductive part 30 may be exposed from theinsulating layer 28 in the thinning process.

Subsequently, the semiconductor substrate 10 is cut (for example, bydicing) into pieces (a semiconductor device 50) as shown in FIG. 3D. Itmay be cut along between one integrated circuit 12 and anotherintegrated circuit 12 which are placed next to each other. Thesemiconductor substrate 10 may be cut on a reinforcing member 60. Morespecifically, the reinforcing member 60 may be provided on one of thefirst surface 20 or the second surface 21 of the semiconductor substrate10. The semiconductor substrate 10 is cut from the other surface. Thereinforcing member 60 may include a tape 62 which is applied to one ofthe first surface 20 or the second surface 21, and a supporting member64 which supports the tape 62. The tape 62 may be hardened by energy(for example, ultraviolet curing). The supporting member 64 may beformed to be ring shaped and support a peripheral portion of the tape62. As an exemplary modification, the supporting member may be a plate(for example, a glass plate or a plastic plate) which supports thesemiconductor substrate 10 from one of the first surface 20 side or thesecond surface 21 side (the plate is not shown in the figures). Anadhesive agent may be applied on the plate so as to temporarily glue andretain the semiconductor substrate 10.

Instead of (or together with) the above-mentioned inspection process(see FIG. 3A) that comes before the thinning process, an inspectionprocess checking an electric property of the semiconductor substrate 10may be conducted before cutting the semiconductor substrate followingthe thinning process. In this way, at least defects caused in thethinning process can be found. Also, the inspection process may beconducted on the above-mentioned reinforcing member 60. This makes iteasier to handle the semiconductor substrate 10 (for example, transportto an inspection stage), since the semiconductor substrate 10 isreinforced with the reinforcing member 60. More specifically, it mayprevent the semiconductor substrate 10 from being impaired (cracking andthe like). Other details in the inspection process may be the same asstated above.

In the cutting process as shown in FIG. 3D, a cutter 66 (for example, adicer) or a laser (for example, a CO2 laser or a YAG laser) may be usedto cut the semiconductor substrate 10. The cutting process may becarried out by mechanical cutting.

As shown in FIG. 4, the method of manufacturing a semiconductor deviceaccording to the exemplary embodiment also includes a step of stackingmore than one semiconductor device 50 manufactured in theabove-mentioned way. Finally, a semiconductor device 1 having a stackstructure is made. One semiconductor device 50 placed upper and anothersemiconductor device 50 placed lower may be electrically coupled throughthe conductive part 30. One conductive part 30 may be electricallycoupled to another conductive part 30 through a brazing material. Aplurality of semiconductor devices are sealed with a sealing member 52.A wiring layer 54 (a relocation wiring layer) may be formed in thesemiconductor device 50 that is on the out most side (the one at thebottom in FIG. 4). A part of the wiring layer 54 (for example, a landportion) may be formed on a resin layer 56. An external terminal 58 (forexample, a solder ball) may be formed on a part of the wiring layer 54(for example, a land portion). In the example shown in FIG. 4, thesemiconductor device 1 is electrically coupled to a wiring pattern 1100in a circuit substrate 1000.

According to the exemplary embodiment of the present invention, sincethe electric property of the semiconductor substrate 10 is checked afterthe formation process of the conductive part 30 is completed, theinspection process prevents and/or reduces adversely affectingreliability in the formation process of the conductive part 30.Consequently, reliability of the method of forming a semiconductordevice will be enhanced and/or improved. Other advantages are asdescribed above. As examples of electronic equipment including asemiconductor device manufactured by the method according to theexemplary embodiments of the present invention, a notebook computer 2000is shown in FIG. 5, and a mobile phone 3000 is shown in FIG. 6.

The present invention is not limited to the exemplary embodimentsdescribed above but applied to various kinds of exemplary modificationswithin the scope and spirit of the present invention. For example, thepresent invention includes a structure which is substantially the sameas the above-mentioned structure in the exemplary embodiments (forexample, a structure whose function, method and results are the same asthose of the present invention, or a structure whose purposes andresults are the same as those of the present invention). Also, thepresent invention includes a structure which is described in theabove-mentioned exemplary embodiments and whose nonessential part issubstituted. The present invention also includes a structure having thesame effects as those of the above-mentioned exemplary embodiments, anda structure which can attain the same purposes as those of theabove-mentioned exemplary embodiments. Further, the present inventionincludes other structures in which related art methods and techniquesare incorporated into the above-mentioned exemplary embodiments.

1. A method of manufacturing a semiconductor device, comprising: (a)forming a conductive part within a concave portion that is formed in afirst surface of a semiconductor substrate having an integrated circuit;(b) thinning the semiconductor substrate by removing a part of a secondsurface of the semiconductor substrate so as to make the conductive partpenetrate from the first surface to the second surface; (c) cutting thesemiconductor substrate into pieces; and (d) inspecting an electricproperty of the semiconductor substrate through the conductive partafter step (a) is finished.
 2. The method of manufacturing asemiconductor device according to claim 1, further including forming theconductive part to have a brazing layer on a top surface of theconductive part in step (a).
 3. The method of manufacturing asemiconductor device according to claim 1, further including forming theconductive part to have a gold layer on a top surface of the conductivepart in step (a).
 4. The method of manufacturing a semiconductor deviceaccording to claim 1, further including conducting the inspectingprocess before step (b).
 5. The method of manufacturing a semiconductordevice according to claim 1, step (c) further comprising: (c1) providinga reinforcing member on the semiconductor substrate; (c2) conducting theinspecting process; and (c3) cutting the semiconductor substrate.
 6. Themethod of manufacturing a semiconductor device according to claim 5,further comprising applying a tape to one of the first surface or thesecond surface of the reinforcing member and a supporting member whichsupports the tape.
 7. The method of manufacturing a semiconductor deviceaccording to claim 1, further including: stacking a plurality ofsemiconductor devices which are manufactured by the method according toclaim 1.